Keynote Speaker

Roman Obermaisser

University of Siegen, Germany



Title: Networked Multi-Core Chips in Mixed Criticality Systems


Mixed-criticality architectures with support for modular certification make the integration of application subsystems with different safety assurance levels both technically and economically feasible. Strict segregation of these subsystems is a key requirement to avoid fault propagation and unintended side-effects due to integration. Also, mixed-criticality architectures must deal with the heterogeneity of subsystems that differ not only in their criticality, but also in the underlying computational models and the timing requirements. Non safety-critical subsystems often demand adaptability and support for dynamic system structures, while certification standards impose static configurations for safety-critical subsystems. Several aspects such as time and space partitioning, heterogeneous computational models and adaptability were individually addressed at different integration levels including distributed systems, the chip-level and software execution environments. However, a holistic architecture for the seamless mixed-criticality integration encompassing distributed systems, multi-core chips, operating systems and hypervisors is an open research problem. This presentation discusses the state-of-the-art of mixed-criticality systems and presents research challenges towards a hierarchical mixed-criticality platform with support for strict segregation of subsystems, heterogeneity and adaptability.

Biodata: Prof. Dr. Roman Obermaisser is full professor at the Division for Embedded Systems of University of Siegen. He has studied computer sciences at Vienna University of Technology, and received the Master’s degree in 2001. In February 2004, Roman Obermaisser has finished his doctoral studies in Computer Science with Prof. Hermann Kopetz at Vienna University of Technology as research advisor. In July 2009, Roman Obermaisser has received the habilitation (“Venia docendi”) certificate for Technical Computer Science. His research work focuses on system architectures for distributed embedded real-time systems. He wrote a book on an integrated time-triggered architecture published by Springer-Verlag, USA. He is the author of several journal papers and conference publications. He has also participated in numerous EU research projects (e.g., SAFEPOWER, universAAL, DECOS, NextTTA) and was the coordinator of the European research projects DREAMS, GENESYS and ACROSS.